An Event-Based Neural Network Architecture with Content Addressable Memory

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Author(s): Sivaganesan S (Karpagam Academy of Higher Education, Tamil Nadu, India), Maria Antony S (KIT-Kalaignarkarunanidhi Institute of Technology, Tamil Nadu, India)and Udayakumar E (KIT-Kalaignarkarunanidhi Institute of Technology, Tamil Nadu, India)
Copyright: 2020
Volume: 11
Issue: 1
Pages: 18
Source title: International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
Editor(s)-in-Chief: Sergey Balandin (FRUCT Oy, Finland)
DOI: 10.4018/IJERTCS.2020010102

Keywords: Information Science Reference / Media & Communications / Networking and Telecommunications / Telecommunications

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Abstract

A hybrid analog/digital very large-scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights was designed. The synaptic weight values are stored in an asynchronous module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. It acts as a transceiver, receiving asynchronous events for input, performing neural computations with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the address event representation (AER). Using this representation, it is possible to interface the device to a workstation or a microcontroller and explore the effect of different types of spike-timing dependent plasticity (STDP) learning algorithms for updating the synaptic weights values in the CAM module.

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An Event-Based Neural Network Architecture with Content Addressable Memory

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