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Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip

Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip
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Author(s): Parisa Khadem Hamedani (The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada), Natalie Enright Jerger (The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada), Shaahin Hessabi (Department of Computer Engineering, Sharif University of Technology, Tehran, Iran) and Hamid Sarbazi-Azad (Department of Computer Engineering, Sharif University of Technology, Tehran, Iran, & Institute for Research in Fundamental Sciences (IPM), Tehran, Iran)
Copyright: 2013
Volume: 4
Issue: 3
Pages: 19
Source title: International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)
DOI: 10.4018/jaras.2013070103

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Abstract

This paper proposes three ILP-based static thermal-aware mapping algorithms for 3D Networks-on-Chip (NoC). With these three mapping algorithms, the authors explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, the authors show that the first algorithm, an optimal one, is not suitable for 3D NoCs. Therefore, the authors develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. According to simulation results, mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This peak temperature reduction comes at the price of a higher power-delay product. The authors’ exploration shows that considering power balancing early in the mapping algorithm does not affect chip temperature. Moreover, the authors show that considering explicit performance constraints in the thermal mapping has no major effect on performance.

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