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A Road Map for the Validation, Verification and Testing of Discrete Event Simulation
Abstract
The aim of this chapter is to give an elaborate reasoning for the motivation for Validation, Verification, and Testing (VV&T) in Simulation. Thereby, defining Simulation in its broadest aspect as embodying a certain model to represent the behavior of a system, whether that may be an economic or an engineering one, with which conducting experiments is attainable. Such a technique enables the management, when studying models currently used, to take appropriate measures and make fitting decisions that would further complement today’s growth sustainability efforts, apart from cost decrease, as well as service delivery assurance. As such, the Computer Simulation technique contributed in cost decline; depicting the “cause and effect,” pinpointing task-oriented needs or service delivery assurance, exploring possible alternatives, identifying problems, as well as proposing streamlined, measurable, deliverable, solutions, providing the platform for change strategy introduction, introducing potential prudent investment opportunities, and finally, providing a safety net when conducting training courses. Yet, the simulation development process is hindered due to many reasons. Like a rose, Computer Simulation technique, does not exist without thorns, of which the length, as well as the communication during the development life cycle. Simulation reflects real-life problems; hence, it addresses numerous scenarios with handful of variables. Not only is it costly, as well as liable for human judgment, but also, the results are complicated and can be misinterpreted.
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