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The Ultimate Data Flow for Ultimate Super Computers-on-a-Chip
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Author(s): Veljko Milutinović (Indiana University, USA), Miloš Kotlar (School of Electrical Engineering, University of Belgrade, Serbia), Ivan Ratković (Esperanto Technologies, Serbia), Nenad Korolija (Independent Researcher, Serbia), Miljan Djordjevic (University of Belgrade, Serbia), Kristy Yoshimoto (Indiana University, USA)and Mateo Valero (BSC, Spain)
Copyright: 2021
Pages: 7
Source title:
Handbook of Research on Methodologies and Applications of Supercomputing
Source Author(s)/Editor(s): Veljko Milutinović (Indiana University, Bloomington, USA)and Miloš Kotlar (University of Belgrade, Serbia)
DOI: 10.4018/978-1-7998-7156-9.ch021
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Abstract
This chapter starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used machine learning algorithms needed in bandwidth-bound applications, and a flexible-structure reprogrammable accelerator for less frequently used machine learning algorithms needed in latency-critical applications. The future SuperComputers-on-a-Chip should include effective interfaces to specific external accelerators based on quantum, optical, molecular, and biological paradigms, but these issues are outside the scope of this chapter.
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