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A Glimpse of Hardware Design Approaches
Abstract
In this chapter, the authors have described that in order to design the vein enhancement and feature extraction algorithm, different modules such as DSP, embedded processor, hardware accelerator, and FPGA are implemented. Further, it has also been revealed in this chapter that the performance of the vein algorithm implemented on the Nios-II and DSP processor is not considered fast though the DSP processor is designed for signal processing applications. The FPGA is an acceptable choice for researchers due to low-cost factors. The FPGA is implemented for the hardware design of the vein algorithm. However, the performance result was not fast. Furthermore, to cater to the need for better performance, innovative hardware design architecture is the need of the time. It is observed that if there are considerable calculations in the algorithm, the optimization of the algorithm with the parallel processing capabilities of hardware will be a good choice as it can mitigate the error of the calculations.
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