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CNTFET-Based Memory Design

CNTFET-Based Memory Design
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Author(s): Shashi Bala (Chandigarh Group of Colleges, Landran, India), Mamta Khosla (National Institute of technology, Jalandhar, India) and Raj Kumar (University Institute of Engineering and Technology, Panjab University, Chandigarh, India)
Copyright: 2020
Pages: 21
Source title: Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET)
Source Author(s)/Editor(s): Balwinder Raj (National Institute of Technical Teachers Training and Research, Chandigarh, India), Mamta Khosla (Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India) and Amandeep Singh (National Institute of Technology, Srinagar, India)
DOI: 10.4018/978-1-7998-1393-4.ch002

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Abstract

As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.

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