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Design of Reconfigurable Architectures for Steganography System
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Author(s): Sathish Shet (JSS Academy of Technological Education, India), A. R. Aswath (Dayananda Sagar College of Engineering, India), M. C. Hanumantharaju (BMS Institute of Technology and Management, India)and Xiao-Zhi Gao (Aalto University School of Electrical Engineering, Finland)
Copyright: 2017
Pages: 24
Source title:
Applied Video Processing in Surveillance and Monitoring Systems
Source Author(s)/Editor(s): Nilanjan Dey (Techno India College of Technology, Kolkata, India), Amira Ashour (Tanta University, Egypt)and Suvojit Acharjee (National Institute of Technology Agartala, India)
DOI: 10.4018/978-1-5225-1022-2.ch007
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Abstract
The most crucial task in real-time processing of image or video steganography algorithms is to reduce the computational delay and increase the throughput of a steganography embedding and extraction system. This problem is effectively addressed by implementing steganography hiding and extraction methods in reconfigurable hardware. This chapter presents a new high-speed reconfigurable architectures that have been designed for Least Significant Bit (LSB) and multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASIC) implementation. Typical architectures of LSB steganography comprises secret message length finder, message hider, extractor, etc. The architectures may be realized either by using traditional hardware description languages (HDL) such as VHDL or Verilog. The designed architectures are synthesizable in FPGAs since the modules are RTL compliant. Before the FPGA/ASIC implementation, it is convenient to validate the steganography system in software to verify the concepts intended to implement.
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