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Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect
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Author(s): Ram Prasad Mohanty (National University of Singapore, Singapore), Ashok Kumar Turuk (National Institute of Technology, India)and Bibhudatta Sahoo (National Institute of Technology, India)
Copyright: 2016
Pages: 16
Source title:
Emerging Research Surrounding Power Consumption and Performance Issues in Utility Computing
Source Author(s)/Editor(s): Ganesh Chandra Deka (Regional Vocational Training Institute (RVTI) for Women, India), G.M. Siddesh (Ramaiah Institute of Technology, India), K. G. Srinivasa (M S Ramaiah Institute of Technology, Bangalore, India)and L.M. Patnaik (IISc, Bangalore, India)
DOI: 10.4018/978-1-4666-8853-7.ch009
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Abstract
The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.
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