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Review on 60GHz Low Noise Amplifier for Low Power and Linearity
Abstract
In the extremely high frequency radio spectrum of 30-300 GHz, the band from 57-64 GHz has been de-regulated. The biggest challenge in designing products at this frequency is the design of CMOS based transceiver circuit components. This chapter deals with the review of 60 GHz LNA design. LNA was chosen as this is the first component of the receiver circuit and its performance affects the transceiver efficiency. In this chapter the review is done on 60GHz LNA's design addressing the linearization, and low power challenges. To address these challenges, in literature there are many LNA architectures such as simple cascode topology, Current reuse topology etc. The major advantage of current reuse topology is its load transistor shares the same bias current of driver which results in reduced power dissipation by maintaining the maximum gain. The main objective of this chapter is to address gain, power dissipation and linearization challenges by reviewing the different current reuse architectures and linearization techniques used to implement 60GHz LNA.
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