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Architectural Support for Enhancing Critical Secrets Protection in Chip-Multiprocessors

Architectural Support for Enhancing Critical Secrets Protection in Chip-Multiprocessors
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Author(s): Lu Peng (Louisiana State University, USA), Li Yang (University of Tennessee at Chattanooga, USA) and Balachandran Ramadass (Louisiana State University, USA)
Copyright: 2011
Pages: 12
Source title: Pervasive Information Security and Privacy Developments: Trends and Advancements
Source Author(s)/Editor(s): Hamid Nemati (The University of North Carolina at Greensboro, USA)
DOI: 10.4018/978-1-61692-000-5.ch012

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Abstract

Security has been considered as an important issue in processor design. Most of the existing designs of security handling assume the chip as a single secure unit. However, such assumption is vulnerable to exposure resulted from a central failure point. This chapter proposes a secure Chip-Multiprocessor architecture (SecCMP) to handle security related problems such as key protection and core authentication in multi-core systems. Matching the nature of multi-core systems, a distributed threshold secret sharing scheme is employed to protect critical secrets. A critical secret (e.g., encryption key) is divided into multiple shares and distributed among multiple cores instead of being kept a single copy in one core that is sensitive to exposure. The proposed SecCMP can not only enhance the security and fault-tolerance in secret protection but also support core authentication. SecCMP is designed to be an efficient and secure architecture for CMPs.

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