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Formal Reliability Analysis of Embedded Computing Systems
Abstract
The accurate reliability assessment of embedded systems has become a concern of overwhelming importance with their increasingly ubiquitous usage in safety-critical domains like transportation, medicine, and nuclear power plants. Traditional reliability analysis approaches of testing and simulation cannot guarantee accurate result and thus there is a growing trend towards developing precise mathematical models of embedded systems and to use formal verification methods to assess their reliability. This chapter is mainly focused towards this emerging trend as it presents a formal approach for the reliability assessment of embedded computing systems using a higher-order-logic theorem prover (HOL). Besides providing the formal probability theory based fundamentals of this recently proposed technique, the chapter outlines a generic reliability analysis methodology for embedded systems as well. For illustration purposes, two case studies have been considered, i.e., analyzing the reparability conditions for a reconfigurable memory array in the presence of stuck-at and coupling faults and assessing the reliability of combinational logic based digital circuits.
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