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Low-Power Methodologies and Strategies in VLSI Circuits
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Author(s): Preethi (Presidency University, India), Sapna R. (Presidency University, India)and Mohammed Mujeer Ulla (Presidency University, India)
Copyright: 2023
Pages: 16
Source title:
Energy Systems Design for Low-Power Computing
Source Author(s)/Editor(s): Rathishchandra Ramachandra Gatti (Sahyadri College of Engineering and Management, India), Chandra Singh (Sahyadri College of Engineering and Management, India), Srividya P. (RV College of Engineering, India)and Sandeep Bhat (Sahyadri College of Engineering and Management, India)
DOI: 10.4018/978-1-6684-4974-5.ch001
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Abstract
Due to the fact that low-power gadgets are currently dominating the electronics sectors, researchers are studying their design. Power management is a crucial parameter for designing VLSI circuits since it is essential for estimating the performance of devices, especially those utilized in biomedical and IoT applications. To achieve greater performance, designing a low-power system on a IC is becoming increasingly challenging due to the reduction in size of chip, increases in chip density, and rise in device complexity. Furthermore, for the less than 90 nm node, due to its increasingly complicated design, the total power factor on a chip is turning into a significant difficulty. Leakage current also has a significant effect on how low-power VLSI devices manage their power. Leakage and dynamic power reduction are increasingly being prioritized in VLSI circuit design in order to improve the battery life of electronic portable devices. The many methodologies, tactics, and power management schemes that can be employed for the design of low-power circuit systems are discussed in this chapter.
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